There is increasing need for small-capacity non-volatile ROMs in storing security codes in LSI (Large-Scale Integration) oriented toward digital appliances and mobile telephones and for trimming gradation adjustment parameters in LCDs (Liquid Crystal Displays) and temperature parameters in control of TCXOs (Temperature-Compensated Crystal Oscillators). In a non-volatile ROM, there are many cases in which a separate chip of an EEPROM (Electronically Erasable and Programmable Read-Only Memory) is mounted by an SIP (System in Package). In recently disclosed techniques, a non-volatile ROM can be formed through a standard CMOS (Complementary Metal-Oxide Semiconductor) process that does not include additional steps. For example, antifuse-type memories are disclosed in Patent Documents 1, 2 and Non-Patent Document 1, etc.
For example, as illustrated in FIG. 8, an antifuse memory has a select transistor 108 in which N+ source/drain diffusion layers 103 are formed on both sides of the channel of a P-type semiconductor substrate 101 and a gate electrode 106 is formed on the channel via a thick gate insulating film 104. The memory further includes an antifuse 109 in the area adjacent to the select transistor 108. The antifuse 109 has a fuse upper electrode 107, which comprises polysilicon, formed via a thin gate insulating film 105 thinner than the thick gate insulating film 104 on the semiconductor substrate 101 between a fuse lower-electrode diffusion layer 127 connected to one of the source/drain diffusion layers 103 and an element isolation region 102 formed in the semiconductor substrate 101. The other source/drain diffusion layer 103 is electrically connected to a bit line BL via a bit contact 110 buried in a hole formed in an interlayer insulating film 111. The gate electrode 106 is electrically connected to a word line WR, and the fuse upper electrode 107 is electrically connected to a plate line WP.
The write operation of this type of antifuse memory cell is performed by breaking down the thin gate insulating film 105 of the antifuse 109. When the thin gate insulating film 105 is broken down by applying a high positive potential to the N+ fuse lower-electrode diffusion layer 127 that will become the lower electrode of the antifuse 109, insulation breakdown is induced while hot carriers due to avalanche breakdown or a band-to-band tunnel, etc., are injected into the thin gate insulating film 105. As a result, breakdown time is unstable, variations tend to occur and reliability tends to decline. For this reason, the applied potential is set so as to suppress the generation of hot carriers from the vicinity of the source/drain diffusion layer 103 at the time of breakdown of the thin gate insulating film 105.
For example, in a case where a memory cell is selected/non-selected in a write operation, as shown in FIG. 9, a potential Vwp1 of a select plate line WP1 in a select memory cell 113 is made a high positive breakdown potential VPP, a potential Vwr1 of a select word line WR1 is made VPP/2 and a potential Vb11 of a select bit line BL1 is made 0 V, whereby the thin gate insulating film 105 is broken down without applying potential to the fuse lower-electrode diffusion layer 127. In a non-select memory cell 114, a potential Vb12 of a non-select bit line BL2 is made VPP/2 and a suppressed potential is applied so as not to cause gate breakdown of the antifuse.
In the case of a read operation, it is important in terms of reliability that the current that flows through the antifuse of the select memory cell 113 be made to have the same direction as that of the write operation. However, readout of the select memory cell 113 is performed by placing the potential Vwp1 of the select plate line WP1 at a power supply potential VddIO of an IO unit, placing the potential Vwr1 of the select word line WR1 of the select transistor at the power supply potential Vdd, placing the potential Vb11 of the select bit line BL1 at 0 V and placing the potential Vb12 of the non-select bit line BL2 at Vdd which is the same as that of the select word line WR1 in such a manner that electrons will flow from the upper electrode of the antifuse into the bit line via the lower electrode and select transistor.
[Patent Document 1] U.S. Pat. No. 6,798,693
[Patent Document 2] Japanese Patent Kokai Publication No. JP-P2001-308283A
[Non-Patent Document 1] Bernard Aronson (Kilopass), “A Novel embedded OTPNVM Using Standard Foundry CMOS Logic Technology”, IEDM2006 (International Electron Devices Meeting), USA, Institute of Electrical and Electronic Engineers (IEEE), 2006, p. 24.